I’ve always had a knack for FPGAs and hardware description languages. I was given my first opportunity in 2018 to learn and work with VHDL as a reliability researcher at the IRT national laboratory in France. I acted as a liaison between a research group in Israel and was tasked with translating their results into a repeatable process for testing chips. The research group in Israel had developed a method for rapidly testing relative failure mechanism impact in deep sub-micron transistor nodes. I prototyped their methodology on a Xilinx SoC using Vivado and Xilinx SDK.

Between October 2020 and June 2021 I worked with Sawback technologies to prototype a ground penetrating radar. That radar used a Xilinx SoC that likewise required coding in Vivado and Xilinx SDK. Then during the Fall of 2021 and Spring of 2022 I pursued two semesters of a masters degree and learned how to use Intel Quartus Lite with Cyclone IV FPGAs. Here’s a link to the YouTube tutorials I made for that chip.

Early at ManTech (2020 to 2022) I performed an FPGA market study that helped inform our choice of a Pentek board. I also worked on writing C++ drivers for Pentek SoCs at ECS in 2023.